Search - verilog dds

[VHDL-FPGA-Verilog] high_speed_tap8_DDS

Description: 用verilog编写的高速8路并行dds模块，用于与高速da(1ghz或以上)接口产生任意频率正弦波，模块已经经过工程验证，用于产品中。-Verilog prepared with high-speed 8-way parallel dds modules for use with high-speed da (1ghz or above) interface have any frequency sine wave, the module has been proof for the products.
Platform: | Size: 5120 | Author: yangyu | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 这里边有EDA设计常用模块的源代码，FFT,DDS PS2_keyboard，VGA等，有学FPGA的就参考一下吧-Here the design of commonly used modules have EDA source code, FFT, DDS PS2_keyboard, VGA and so on, have places on the FPGA reference yourself
Platform: | Size: 208896 | Author: li | Hits:

[source in ebook] AD9910Driver

Description: DDS之AD9910驱动源码，控制器ARM ADuc7026.-DDS source of the AD9910 driver, controller ARM ADuc7026.
Platform: | Size: 139264 | Author: 彭梁栋 | Hits:

[Software Engineering] dds

Description: 自己收集的一些关于DDS的文章，主要讲述了DDS原理以及如何利用verilog实现DDS-To collect some of their articles on the DDS, the main principle on the DDS and how to use DDS to achieve verilog
Platform: | Size: 3298304 | Author: 刘小平 | Hits:

[SCM] dual_ram

Description: FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
Platform: | Size: 513024 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] cordicDDS

Description: Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。-DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.
Platform: | Size: 7168 | Author: 王王 | Hits:

[VHDL-FPGA-Verilog] learn_dds

Description: 基于quartus ii 9.0的简易dds波形发生器，可以产生正弦，方波，三角波，可变幅，可变频。非常适合学习使用，使用时请按自己的芯片和引脚设置-Quartus ii 9.0 Based on dds simple waveform generator can produce sine, square, triangle wave can be amplitude, frequency can be. Very suitable for learning to use, when used by their chip and pin set
Platform: | Size: 732160 | Author: 陈东旭 | Hits:

[Post-TeleCom sofeware systems] qam_64

Description: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Platform: | Size: 1024 | Author: zhujing | Hits:

[Compress-Decompress algrithms] asias_dds

Description: 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency
Platform: | Size: 31744 | Author: david | Hits:

[Embeded Linux] 83390078DDS

Description: DDS的工作原理是以数控振荡器的方式产生频率、相位可控制的正弦波。电路一般包括基准时钟、频率累加器、相位累加器、幅度/相位转换电路、D/A转换器和低通滤波器（LPF）。频率累加器对输入信号进行累加运算，产生频率控制数据X（frequency data或相位步进量）。相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的2进制码进行累加运算，是典型的反馈电路，产生累加结果Y。幅度/相位转换电路实质上是一个波形寄存器，以供查表使用。读出的数据送入D/A转换器和低通滤波器。-DDS works the way we are digitally controlled oscillator frequency, phase controlled sine wave. Circuits generally include reference clock, frequency accumulator, phase accumulator, amplitude/phase converter circuit, D/A converter and low-pass filter (LPF). The frequency accumulator to accumulate the input signal operation to produce the frequency control data X (frequency data or phase stepping volume). From the N-bit phase accumulator and the N-bit full adder cascade accumulation register is made on behalf of the frequency of the two binary codes accumulation operation, is a typical feedback circuit, resulting in cumulative results of Y. Amplitude/phase converter circuit is essentially a waveform register for look-up table to use. Read out the data into the D/A converter and low pass filter.
Platform: | Size: 44032 | Author: 394177191 | Hits:

[VHDL-FPGA-Verilog] dds_final

Description: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Platform: | Size: 1638400 | Author: nostalgia | Hits:

[VHDL-FPGA-Verilog] AD9954_test

Description: AD公司DDS芯片AD9954的Verilog测试程序-VerilogHDL test program of DDS chip--AD9954 ,producted by AD company
Platform: | Size: 2068480 | Author: ch | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 该程序使用Verilog语言，可以生成dds正余弦信号-The program uses the Verilog language, can generate sine and cosine signals dds
Platform: | Size: 6144 | Author: 王丽 | Hits:

[Other] dds

Description: 包含完整的dds产生的Verilog程序和test 文件-Contains the complete dds generated Verilog program and test files
Platform: | Size: 6110208 | Author: fqzxw | Hits:

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[VHDL-FPGA-Verilog] high_speed_tap8_DDS

[VHDL-FPGA-Verilog] EDA

[source in ebook] AD9910Driver

[Software Engineering] dds

[SCM] dual_ram

[VHDL-FPGA-Verilog] dds_easy

[VHDL-FPGA-Verilog] cordicDDS

[VHDL-FPGA-Verilog] learn_dds

[Post-TeleCom sofeware systems] qam_64

[Compress-Decompress algrithms] asias_dds

[Embeded Linux] 83390078DDS

[VHDL-FPGA-Verilog] dds_final

[VHDL-FPGA-Verilog] AD9954_test

[VHDL-FPGA-Verilog] cordic

[Other] dds

[VHDL-FPGA-Verilog] DDS_Set

[VHDL-FPGA-Verilog] Verilog

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] cordic

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